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KM48C512D cmos dram high speed this is a family of 524,288 x 8 bit extended data out mode cmos drams. extended data out mode offers high speed random access of memory cells within the same row. access time (-4), power consumption(normal or low power) and package type(soj or tsop-ii) are optional features of this family. all of this family have cas -before- ras refresh, ras -only refresh and hidden refresh capabilities. furthermore, self-refresh operation is available in l-version. this 512kx8 edo mode dram family is fabricated using samsung s advanced cmos process to realize high band-width, low power consumption and high reliability. it may be used as main memory unit for microcomputer, personal computer and portable machines. ? part identification - KM48C512D/dl (5v, 1k ref.) ? fast page mode operation ? byte read/write operation ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? self-refresh capability (l-ver only) ? ttl compatible inputs and outputs ? early write or output enable controlled write ? jedec standard pinout ? available in 28-pin soj 400mil & 28-pin tsop(ii) 400mil packages ? dual +5v 10% power supply control clocks vbb generator refresh timer refresh control refresh counter row address buffer col. address buffer row decoder column decoder ras cas w vcc vss dq0 to dq7 a0 ~ a9 a0 ~ a8 memory array 524,288 x8 cells samsung electronics co., ltd. reserves the right to change products and specifications without notice. high speed 512k x 8bit cmos dynamic ram with with fast page mode description features functional block diagram ? refresh cycles part no. v cc refresh cycle refresh period normal l-ver c512d 5v 1k 16ms 128ms ? perfomance range speed t rac t cac t rc t pc -4 40ns 12ns 75ns 28ns ? active power dissipation speed active power dissipation -4 770 unit : mw s e n s e a m p s & i / o data out buffer data in buffer oe
KM48C512D cmos dram high speed 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pin configuration (top views) pin name pin function a0 - a9 address inputs dq0 - 7 data in/out v ss ground ras row address strobe cas column address strobe w read/write input oe data output enable v cc power(+5v) n.c no connection v cc dq0 dq1 dq2 dq3 n.c w ras a9 a0 a1 a2 a3 v cc v ss dq7 dq6 dq5 dq4 cas oe n.c a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (soj) (tsop-ii) v cc dq0 dq1 dq2 dq3 n.c w ras a9 a0 a1 a2 a3 v cc v ss dq7 dq6 dq5 dq4 cas oe n.c a8 a7 a6 a5 a4 v ss ? km48c514dj ? km48c514dt
KM48C512D cmos dram high speed absolute maximum ratings * permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol rating units voltage on any pin relative to v ss v in, v out -1.0 to +7.0 v voltage on v cc supply relative to v ss v cc -1.0 to +7.0 v storage temperature tstg -55 to +150 c power dissipation p d 1 w short circuit output current i os address 50 ma recommended operating conditions (voltage referenced to vss, t a = 0 to 70 c) *1 : v cc +2.0/20ns(5v), pulse width is measured at v cc *2 : -2.0v/20ns(5v), pulse width is measured at v ss parameter symbol min typ max units supply voltage v cc 4.5 5.0 5.5 v ground v ss 0 0 0 v input high voltage v ih 2.4 - v cc +1.0 *1 v input low voltage v il -1.0 *2 - 0.8 v dc and operating characteristics (recommended operating conditions unless otherwise noted.) parameter symbol min max units input leakage current (any input 0 v in v in +0.5v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-5ma) v oh 2.4 - v output low voltage level(i ol =4.2ma) v ol - 0.4 v
KM48C512D cmos dram high speed *note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 , i cc3 , i cc6 and i cc7, address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one fast page mode cycle time, t pc . dc and operating characteristics i cc1 * : operating current ( ras and cas , address cycling @ t rc =min.) i cc2 : standby current ( ras = cas = w =v ih ) i cc3 * : ras -only refresh current ( cas =v ih , ras , address cycling @ t rc =min.) i cc4 * : fast page mode current ( ras =v il , cas , address cycling @ t pc =min.) i cc5 : standby current ( ras = cas = w =v cc -0.2v) i cc6 * : cas -before- ras refresh current ( ras and cas cycling @ t rc =min.) i cc7 : battery back-up current, average power supply current, battery back-up mode input high voltage(v ih )=v cc -0.2v, input low voltage(v il )=0.2v, cas =0.2v, dq=don t care, t rc =31.25us, t ras =t ras min~300ns i ccs : self refresh current ras = cas =v il , w = oe =a0 ~ a9 =v cc -0.2v or 0.2v, dq0 ~ dq7=v cc -0.2v, 0.2v or open symbol power max units i cc1 don t care 140 ma i cc2 don t care 2 ma i cc3 don t care 140 ma i cc4 don t care 110 ma i cc5 normal l 1 150 ma ua i cc6 don t care 140 ma i cc7 l 300 ua i ccs l 200 ua (recommended operating conditions unless otherwise noted.)
KM48C512D cmos dram high speed capacitance (t a =25 c, v cc =5v, f=1mhz) parameter symbol min max units input capacitance [a0 ~ a9] c in1 - 5 pf input capacitance [ ras , cas , w , oe ] c in2 - 7 pf output capacitance [dq0 - dq7] c dq - 7 pf test condition : v cc =5.0v 10%, vih/vil=2.8/0.4v, voh/vol=2.0/0.8v parameter symbol -4 units notes min max random read or write cycle time t rc 75 ns read-modify-write cycle time t rwc 111 ns access time from ras t rac 40 ns 3,4,10 access time from cas t cac 12 ns 3,4,5 access time from column address t aa 20 ns 3,10 cas to output in low-z t clz 0 ns 3 output buffer turn-off delay t off 0 9 ns 6 transition time (rise and fall) t t 3 50 ns 2 ras precharge time t rp 25 ns ras pulse width t ras 40 10k ns ras hold time t rsh 12 ns cas hold time t csh 40 ns cas pulse width t cas 12 10k ns ras to cas delay time t rcd 18 28 ns 4 ras to column address delay time t rad 13 20 ns 10 cas to ras precharge time t crp 5 ns row address set-up time t asr 0 ns row address hold time t rah 8 ns column address set-up time t asc 0 ns column address hold time t cah 10 ns column address to ras lead time t ral 20 ns read command set-up time t rcs 0 ns read command hold time referenced to cas t rch 0 ns 8 read command hold time referenced to ras t rrh 0 ns 8 write command set-up time t wcs 0 ns 7 write command hold time t wch 10 ns write command pulse width t wp 10 ns write command to ras lead time t rwl 12 ns write command to cas lead time t cwl 12 ns ac characteristics (0 c t a 60 c, see note 1,2)
KM48C512D cmos dram high speed ac characteristics (continued) parameter symbol -4 units notes min max data set-up time t ds 0 ns 9 data hold time t dh 10 ns 9 refresh period (normal) t ref 16 ms refresh period (l-ver) t ref 128 ms cas to w delay time t cwd 31 ns 7 ras to w delay time t rwd 59 ns 7 column address w delay time t awd 39 ns 7 cas precharge to w delay time t cpwd 44 ns 7 cas set-up time ( cas -before- ras refresh) t csr 10 ns cas hold time ( cas -before- ras refresh) t chr 10 ns ras to cas precharge time t rpc 5 ns cas precharge time ( c -b- r counter test cycle) t cpt 20 ns access time from cas precharge t cpa 25 ns 3 fast page mode cycle time t pc 28 ns fast page read-modify-write cycle time t prwc 67 ns cas precharge time (fast page cycle) t cp 6 ns ras pulse width (fast page cycle) t rasp 40 100k ns ras hold time from cas precharge t rhcp 23 ns oe access time t oea 12 ns oe to data delay t oed 9 ns output buffer turn off delay time from oe t oez 0 9 ns 6 oe command hold time t oeh 12 ns ras pulse width ( c -b- r self refresh) t rass 100 us 11,12,13 ras precharge time ( c -b- r self refresh) t rps 74 ns 11,12,13 cas hold time ( c -b- r self refresh) t chs -50 ns 11,12,13
KM48C512D cmos dram high speed notes an initial pause of 200us is required after power-up followed by any ras -only refresh or cas -before- ras refresh cycles before proper device operation is achieved. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 2 ttl load and 30pf. dout reference level : voh/vol=2.0v/0.8v operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd , t awd and t cpwd are non restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. if neither of the above con- ditions is satisfied, the condition of the data out is indeterminate. either t rch or t rrh must be satisfied for a read cycle. this parameters are referenced to cas falling edge in early write cycles and to w falling edge in oe controlled write cycle and read-modify-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . if t rass 3 100us, then ras precharge time must use t rps instead of t rp . for ras -only refresh and burst cas -before- ras refresh mode, 1024(1k) cycle of burst refresh must be executed within 16ms before and after self refresh, in order to meet refresh specification. for distributed cas -before- ras with 15.6us interval, cas -before- ras refresh should be executed with in 15.6us immedi- ately before and after self refresh in order to meet refresh specification. 7. 6. 5. 10. 9. 8. 11. 3. 2. 1. 4. 12. 13.
KM48C512D cmos dram high speed t crp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq3(7) read cycle column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t aa t oea t cac t clz t rac open data-out t oez t rrh t rch don t care undefined t rcs t off
KM48C512D cmos dram high speed t wcs write cycle ( early write ) note : d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp t ds t dh t wch t cwl t rwl don t care data-in undefined
KM48C512D cmos dram high speed t oed ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp data-in t wp don t care write cycle ( oe controlled write ) note : d out = open t cwl t rwl t ds t dh t oeh undefined
KM48C512D cmos dram high speed ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq3(7) row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care read - modify - wrtie cycle t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address
KM48C512D cmos dram high speed t rch t oez t clz ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq3(7) column address row addr t rhcp t rasp t cas t asc t rad t asr t rah t asc t cah t crp valid don t care fast page read cycle t oez t rrh data-out undefined valid data-out column address column address t rsh t cas t rcd t pc ? t csh t cah t asc t cah ? ? ? t rch ? t rcs t rcs t rcs t oea t cac t oea t cac t oea t cac valid data-out t clz t off t aa t off t aa t clz t off t oez t rac t aa ? ? t cp t cas t rp t cp t ral
KM48C512D cmos dram high speed t asc t cah ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row addr t rhcp t rasp t cas t rad t asr t rah t asc t crp valid don t care fast page write cycle ( early write ) data-in undefined valid data-in t ds note : d out = open column address column address t rsh t cas t rcd t pc ? t csh t cah t cah ? ? ? t wcs t wch t wcs valid data-in ? ? t wp t cwl t wp t wch t wp t wcs t wch t cwl t rwl t cwl t dh t ds t dh t ds t dh ? ? ? t rp t cp t cp t cas t pc t ral t asc
KM48C512D cmos dram high speed t cac t asc t asc ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq3(7) row addr t csh t rasp t asr valid don t care fast page read - modify - write cycle data-out undefined t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t cah t ral t prwc t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t aa t rac t oea t clz t cac t oez t cpwd t oed valid data-in valid data-out valid data-in t clz t ds t oea t aa t dh t ds t oez t oed t rwl t rp t rsh t rah
KM48C512D cmos dram high speed ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t ras t rc t rp t asr t rah t crp don t care ras - only refresh cycle undefined note : w , oe , d in = don t care d out = open t rpc t crp cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t wrp t rpc t rp t cp t chr t csr w v ih - v il - t wrh t off t rpc v oh - v ol - dq0 ~ dq3(7) open
KM48C512D cmos dram high speed t wrh t off ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq3(7) hidden refresh cycle ( read ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp t rcs t aa t oea t cac t clz t rac open don t care t rsh t oez undefined t rc data-out t rp t rp t ras t ral
KM48C512D cmos dram high speed ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) hidden refresh cycle ( write ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp don t care t rsh data-in t wrp t wrh undefined t rc note : d out = open t wch t wp t dh t rp t rp t ras t ds t wcs t ral
KM48C512D cmos dram high speed cas -before- ras refresh counter test cycle ras v ih - v il - cas v ih - v il - a v ih - v il - column address t ras t rsh t chr t ral t csr t cpt t rp t cas t asc t cah read cycle v oh - v ol - data-out dq0 ~ dq3(7) t clz write cycle v ih - v il - data-in dq0 ~ dq3(7) t dh t ds w v ih - v il - t wp t cwd t cwl t rwl read-modify-write t awd v ih - v il - oe t oea t aa t cac t ds t dh valid data-out v i/oh - v i/ol - dq0 ~ dq3(7) don t care undefined v ih - v il - oe t oea t oez oe v ih - v il - t rcs t clz t oez t oed t wrp t wrh t rrh t rch t rcs t cac t aa v ih - v il - w t wrp t wrh t wcs t wch t cwl v ih - v il - w t wp t rwl t wrp t wrh valid data-in t off
KM48C512D cmos dram high speed don t care undefined cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rass t rps t rpc t wrp t chs t rp t cp t csr w v ih - v il - t wrh t off t rpc open v oh - v ol - dq0 ~ dq3(7) test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t rpc t wts t rpc t rp t cp t chr t csr w v ih - v il - t wth t off open v oh - v ol - dq0 ~ dq3(7)
KM48C512D cmos dram high speed 28 soj 400mil 0 . 4 0 0 ( 1 0 . 1 6 ) 0 . 4 3 5 ( 1 1 . 0 6 ) 0 . 4 4 5 ( 1 1 . 3 0 ) 0.730 (18.54) 0.720 (18.30) max 0.741 (18.82) m a x 0 . 1 4 8 ( 3 . 7 6 ) 0.0375 (0.95) 0.050 (1.27) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 . 3 6 0 ( 9 . 1 5 ) 0 . 3 8 0 ( 9 . 6 5 ) min #28 units : inches (millimeters) package dimension 28 tsop(ii) 400mil max 0.047 (1.20) min 0.002 (0.05) 0.020 (0.50) 0.012 (0.30) 0.050 (1.27) 0.037 (0.95) 0.721 (18.31) 0.729 (18.51) 0.741 (18.81) max 0.010 (0.25) 0.004 (0.10) 0 . 4 0 0 ( 1 0 . 1 6 ) 0 . 4 7 1 ( 1 1 . 9 6 ) 0 . 4 5 5 ( 1 1 . 5 6 ) units : inches (millimeters) 0~8 0.030 (0.75) 0.018 (0.45) typ 0.010 (0.25) o

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